1. Field of the Invention
The present invention relates in general to a method for providing an ultrahigh speed bipolar transistor, and more particularly, to an improved method for providing an ultrahigh speed bipolar transistor having a double-layered sidewall composed of polysilicon and an insulating material.
2. Description of the Related Art
In general, ultrahigh speed bipolar transistors are employed in various applications requiring operating frequencies in the range of 10-45 GHz. A typical bipolar transistor is described below with reference to the figures appended.
FIG. 1 is a schematic cross-sectional view of a typical bipolar transistor. An N type epitaxial layer 120 which functions as the collector region is formed on a P.sup.- substrate 100, and a buried layer 110 is disposed between the epitaxial layer 120 and the substrate 100. A base region 130 is formed on the epitaxial layer 120, on which an N.sup.+ emitter region 140 is slightly formed. On the buried layer 110, an N.sup.+ collector sink region 121 is formed in the epitaxial layer 120. The sink region is isolated from the base region 130 by a field oxide film 167 and is electrically connected to a collector electrode 123 through a collector polysilicon layer 122 formed of an N.sup.+ polysilicon. The base region 130 is electrically connected to a base electrode 133 through a base polysilicon layer 131 formed of a P.sup.+ polysilicon, and the emitter region 140 is electrically connected to the emitter electrode 142 through an emitter polysilicon layer 141 formed of an N.sup.+ polysilicon.
The three electrodes 123, 133 and 142 are electrically isolated from one another by oxide films 162 and 164, while the base polysilicon layer 131 is isolated from the emitter polysilicon layer 141 by an oxide film 161 formed on the base polysilicon layer 131, and by an oxide sidewall 151 formed at a side edge of the base polysilicon layer 131 and a side edge of the oxide film 161. On the partial base region 130, P.sup.+ base polysilicon layers 131 and 132 are formed, and are isolated from the emitter polysilicon layer 141 and the collector polysilicon layer 122 by an oxide sidewall 152 and the oxide film 163 formed on the base polysilicon layer 132.
In this bipolar transistor, an operating speed is determined by such values as a maximum oscillation frequency, an emitter coupled logic (ECL) circuit transmission delay, a maximum cut-off frequency, and a base transmission time. These parameters are described in detail below, with reference to FIG. 3, which is a circuit diagram of a common emitter bipolar transistor, and FIG. 4, which is a small signal equivalent circuit diagram including a load resistance.
(A) The Maximum Oscillation Frequency
This is a frequency at which maximum power gain can be obtained in a wide band analog amplifier and a non-saturated logic gate circuit, as well as in small and large signal amplifiers.
In FIGS. 3 and 4, C.sub.jc is a collector-base junction capacitance, C.sub.je is an emitter-base junction capacitance, C.sub.diff =C.sub.bb is a diffusion capacitance, and g.sub.m is a ratio of an output current to an input voltage. If C.sub..pi. =C.sub.je +C.sub.bb, the output resistance r.sub.out is defined as follows: EQU r.sub.out =C.sub..pi. /C.sub.jc g.sub.m (EQ. 1)
From this equation, since the contribution of C.sub..pi. to the input impedance is very small compared with r.sub.bb in high frequency operations, a high frequency power gain G.sub.p can be derived as follows: EQU G.sub.p =i.sub.c.sup.2 R.sub.L /i.sub.b.sup.2 r.sub.bb =G.sub.m.sup.2 R.sub.L /4r.sub.bb .omega..sup.2 C.sub..pi..sup.2 (Eq. 2)
As can be seen from Eq. 2, when the load resistance R.sub.L is equal to the output resistance r.sub.out, a maximum power gain G.sub.p max is obtained. At this time, the maximum power gain G.sub.p max is expressed as follows: EQU G.sub.p max =g.sub.m /4r.sub.bb .omega..sup.2 C.sub..pi. C.sub.jc(Eq. 3)
In Eq. 3, if g.sub.m /2 .pi.C.sub..pi. is replaced with a maximum cut-off frequency f.sub.t, and .omega. with 2 .pi.f, a maximum oscillation frequency f.sub.osc max can be derived as follows: ##EQU1##
From the above, it is clear that the collector-base junction capacitance C.sub.jc must be reduced and the cut-off frequency f.sub.t must be increased in order to obtain the maximum oscillation frequency which yields the maximum power gain.
(B) ECL Transmission Delay
The equation governing an ECL transmission delay is given as follows: EQU t.sub.pd =Ar.sub.bb C.sub.jc +Br.sub.bb C.sub.je +CC.sub.jc (R.sub.L +R.sub.e)+Dr.sub.e C.sub.je +EC.sub.sb (R.sub.L +r.sub.e)+FC.sub.L (R.sub.L +r.sub.e) (Eq. 5)
where A, B, C, D, E and F are proportional constants, C.sub.sb is the collector-substrate junction capacitance, C.sub.L is the interconnection capacitance. The basic assumption made here is that the collector-base junction capacitance must be reduced in order to reduce the ECL transmission delay, since the CC.sub.jc (R.sub.L+ R.sub.e) term is the most important delay component in the right side of Eq. 5.
(C) Maximum Cut-off Frequency
This is one of the most important parameters in estimating the high frequency characteristics of elements.
The small signal current gain of equivalent circuit shown in FIG. 4 can be expressed as follows: EQU h.sub.fe (.omega.)=i.sub.c /i.sub.b =g.sub.m V.sub.be /i.sub.b(Eq. 6)
where v.sub.be /i.sub.b is the input impedance. If this term is replaced with g.sub..pi., then it follows that: EQU g.sub..pi. =dI.sub.b /dV.sub.BE =g.sub.m /h.sub.fe (Eq. 7)
Further, if C.sub..pi. =C.sub.je +C.sub.je +C.sub.bb, from Eqs. 6 and 7, the small signal current gain is obtained as follows: ##EQU2##
From Eq. 8, if deriving the cut-off frequency when h.sub.fe =1, it follows that: EQU f.sub.t =g.sub.m /2 .pi.C.sub..pi. (Eq. 9)
If the cut-off frequency f.sub.t is the reciprocal of a total delay time during the operation of the common emitter circuit including the element, then a higher f.sub.t can be obtained from the following equation derived from Eq. 9. ##EQU3## where C.sub..pi. /g.sub.m is a time constant which depends upon the emitter-base junction capacitance and the collector-base junction capacitance, and [V.sub.t (C.sub.je +C.sub.jc)/I.sub.c ]+t.sub.bb is the transit time of the minority carrier passing through the base region. Therefore, in order to increase f.sub.t, the junction capacitance and the transmission time of the carrier in the base region should be reduced.
(D) Base Transit Time
As mentioned above, the parameters which define the cut-off frequency include the transit time of the minute carrier, the collector-base junction capacitance and the emitter-base junction capacitance. Among these, the most important parameter is the transit time t.sub.bb of the minority carrier passing through the base region, because this is the main source of delay. That is, the collector-base junction capacitance C.sub.jc and the emitter-base junction capacitance C.sub.je are not the principal contributors in the component for determining the maximum cut-off frequency, in comparison with t.sub.bb, when C.sub.jc and C.sub.je are large.
In an NPN transistor, the base transit time is approximately as follows: EQU t.sub.bb .apprxeq.W.sub.b.sup.2 /.eta.D.sub.n (Eq. 11)
where W.sub.b represents base width, .eta. is the function of a base concentration profile and D.sub.n is an electron diffusion coefficient.
When the slope has a sharp slant (highly non-uniform impurity concentration), an accelerated electric field is dynamically generated in the entire base region and .eta. is more than 2, the base transit time is much more decreased.
As mentioned above, the collector-base junction capacitance and the base width should be small, so that the bipolar transistor can be operated at higher speeds. To obtain these structures, using self-aligned approach employing a double-polysilicon process, the base region is formed by self-aligning from the P.sup.+ base polysilicon layer, and the base contact window is formed.
With reference to FIGS. 2A to 2E, the fabrication method of the bipolar transistor illustrated in FIG. 1 is described below, with particular emphasis on the collector-base junction capacitance.
As shown in FIG. 2A, an N.sup.+ buried layer 110 is formed on a P.sup.- substrate 100 using a first mask, and then an N type epitaxial layer 120, which functions as a collector region, is formed on the N.sup.+ buried layer 110. An isolation region (not shown) is then formed to isolate each element, using a second mask, and an N.sup.+ collector sink region 121 is also formed on the buried layer 110 using a third mask. A fourth mask is then used to define a first region 200 and a second region 300, and a LOCOS isolation process is used to form field oxide films 166, 167 and 168 at each end of the first and second regions 200 and 300. Successively, a fifth mask is used to expose a polysilicon region at which the deposition of the P.sup.+ polysilicon should be performed.
As shown in FIG. 2B, this is followed by depositing the P.sup.+ polysilicon and patterning the deposited layer using a sixth mask. The fabricated polysilicon layer 170 thus covers the first region 200 of the epitaxial layer, but not the second region 300.
Insulating material is then deposited and patterned on the polysilicon layer 170 using a seventh mask. The resulting combined layers are then opened, so that the base polysilicon layers 131 and 132, as well as the insulating layer 160, with an aperture 400 formed therebetween, are formed. After this, a thermal-oxidation process is executed to form the oxide film 500 on the bottom of the aperture 400, and a P type impurity such as BF.sub.2 is implanted using an eighth mask, as shown in FIG. 2C.
Deposition of SiO.sub.2 and reactive ion etching (RIE) with respect to the oxide silicon layer are successively performed, so that oxide sidewalls 151 and 152 are formed, which respectively cover the base polysilicon layers 131 and 132, as shown in FIG. 2D.
Next, an etching process, using a ninth mask applied to the insulating layer 160, is performed so as to partially expose the top surface of the collector sink region 21. As shown in FIG. 2E, in the two apertures thus formed, the emitter polysilicon layer 141 and the collector polysilicon layer 122 are respectively formed by depositing an N.sup.+ polysilicon layer and patterning the layer using a tenth mask. An oxide layer (not shown) is deposited accompanying the following diffusion process.
In the diffusion process, the implanted P type impurities and the impurities of the P.sup.+ base polysilicon layer 131 and the N.sup.+ emitter polysilicon layer 141 are diffused into the epitaxial layer 120, thereby forming the base region 130 connected to the base polysilicon layers 131 and 132, and the emitter region 140 connected to the emitter polysilicon layer 141. An eleventh mask is used to pattern the oxide layer, and to reveal the base polysilicon layer 131, the emitter polysilicon layer 141 and the collector polysilicon layer 122.
Then, in a final process not shown, an aluminum layer is deposited and then patterned using a twelfth mask, to thereby form the base electrode, the emitter electrode and the collector electrode, connected to the base polysilicon layer 131, the emitter polysilicon layer 141 and the collector polysilicon layer 122, respectively.
In the conventional fabrication process described above, the boron dopant diffused from the P.sup.+ polysilicon forms the base region. However, this brings problems of lithography technique and configuration. That is, it is difficult to reduce a junction area with the conventional method. Another disadvantage is that when forming the base region using the ion implantation process, it is difficult to obtain a base of small width and a sharp slope concentration. In addition, there is some disadvantage in that masks for forming the base polysilicon layer and for performing the base ion implantation are required when forming the elements.